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BD6085GUL
Datasheet
? Writing protocol
A register address is transferred by the next 1 byte that transferred the slave address and the write-in command. The 3rd
byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register address
is carried out automatically. However, when a register address turns into the last address, it is set to 00h by the next
transmission. After the transmission end, the increment of the address is carried out.
S X X X X X X X 0 A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A
*1
*1
D7 D6 D5 D4 D3 D2 D1 D0 A P
slave address
R/W=0(write)
register address
DATA
register address
increment
DATA
register address
increment
from master to slave
from slave to master
A=acknowledge(SDA LOW)
A=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
*1: Write Timing
? Reading protocol
It reads from the next byte after writing a slave address and R/W bit. The register to read considers as the following address
accessed at the end, and the data of the address that carried out the increment is read after it. If an address turns into the
last address, the next byte will read out 00h. After the transmission end, the increment of the address is carried out.
S X X X X X X X
slave address
1 A D7 D6 D5 D4 D3 D2 D1 D0 A
DATA
D7 D6 D5 D4 D3 D2 D1 D0 A P
DATA
R/W=1(read)
from master to slave
from slave to master
register address
increment
A=acknowledge(SDA LOW)
A=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
register address
increment
? Multiple reading protocols
After specifying an internal address, it reads by repeated START condition and changing the data transfer direction. The
data of the address that carried out the increment is read after it. If an address turns into the last address, the next byte
will read out 00h. After the transmission end, the increment of the address is carried out.
S X X X X X X X 0 A A7 A6 A5 A4 A3 A2 A1 A0 A Sr X X X X X X X 1 A
slave address
register address
slave address
R/W=0(write)
D7 D6 D5 D4 D3D2 D1D0 A
DATA
register address
increment
from master to slave
from slave to master
R/W=1(read)
D7D6 D5D4D3D2D1D0 A P
DATA
register address
increment
A=acknowledge(SDA LOW)
A=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
Sr=repeated START condition
As for reading protocol and multiple reading protocols, please do A(not acknowledge) after doing the final reading
operation. It stops with read when ending by A(acknowledge), and SDA stops in the state of Low when the reading
data of that time is 0. However, this state returns usually when SCL is moved, data is read, and A(not acknowledge)
is done.
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
10/26
TSZ02201-0G3G0C200120-1-2
05.Oct.2012 Rev.001
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